1. Field of the Invention
The invention relates to an apparatus for high performance switching in local area communications networks such as token ring, ATM, ethernet, fast ethernet, and 1 gigabit and 10,000 Mbits/s ethernet environments, generally known as LANs. In particular, the invention relates to a new switching architecture in an integrated, modular, single chip solution, which can be implemented on a semiconductor substrate such as a silicon chip and a switching fabric that allows for rapid communication between the switches.
2. Description of the Related Art
As computer performance has increased in recent years, the demands on computer networks has significantly increased; faster computer processors and higher memory capabilities need networks with high bandwidth capabilities to enable high speed transfer of significant amounts of data. The well-known ethernet technology, which is based upon numerous IEEE ethernet standards, is one example of computer networking technology which has been able to be modified and improved to remain a viable computing technology. A more complete discussion of prior art networking systems can be found, for example, in SWITCHED AND FAST ETHERNET, by Breyer and Riley (Ziff-Davis, 1996), and numerous IEEE publications relating to IEEE 802 standards. Based upon the Open Systems Interconnect (OSI) 7-layer reference model, network capabilities have grown through the development of repeaters, bridges, routers, and, more recently, xe2x80x9cswitchesxe2x80x9d, which operate with various types of communication media. Thickwire, thinwire, twisted pair, and optical fiber are examples of media which has been used for computer networks. Switches, as they relate to computer networking and to ethernet, are hardware-based devices which control the flow of data packets or cells based upon destination address information which is available in each packet. A properly designed and implemented switch should be capable of receiving a packet and switching the packet to an appropriate output port at what is referred to wirespeed or linespeed, which is the maximum speed capability of the particular network.
Basic ethernet wirespeed is up to 10 megabits per second, and Fast Ethernet is up to 100 megabits per second. The newest ethernet is referred to as 10,000 Mbits/s ethernet, and is capable of transmitting data over a network at a rate of up to 10,000 megabits per second. As speed has increased, design constraints and design requirements have become more and more complex with respect to following appropriate design and protocol rules and providing a low cost, commercially viable solution. For example, high speed switching requires high speed memory to provide appropriate buffering of packet data; conventional Dynamic Random Access Memory (DRAM) is relatively slow, and requires hardware-driven refresh. The speed of DRAMs, therefore, as buffer memory in network switching, results in valuable time being lost, and it becomes almost impossible to operate the switch or the network at linespeed.
Furthermore, external CPU involvement should be avoided, since CPU involvement also makes it almost impossible to operate the switch at linespeed. Additionally, as network switches have become more and more complicated with respect to requiring rules tables and memory control, a complex multi-chip solution is necessary which requires logic circuitry, sometimes referred to as glue logic circuitry, to enable the various chips to communicate with each other. Additionally, the means with which the elements communicate with each other can limit the operational speed of the switch if elements are made to wait for those communications.
Referring to the OSI 7-layer reference model discussed previously, the higher layers typically have more information. Various types of products are available for performing switching-related functions at various levels of the OSI model. Hubs or repeaters operate at layer one, and essentially copy and xe2x80x9cbroadcastxe2x80x9d incoming data to a plurality of spokes of the hub. Layer two switching-related devices are typically referred to as multiport bridges, and are capable of bridging two separate networks. Bridges can build a table of forwarding rules based upon which MAC (media access controller) addresses exist on which ports of the bridge, and pass packets which are destined for an address which is located on an opposite side of the bridge. Bridges typically utilize what is known as the xe2x80x9cspanning treexe2x80x9d algorithm to eliminate potential data loops; a data loop is a situation wherein a packet endlessly loops in a network looking for a particular address. The spanning tree algorithm defines a protocol for preventing data loops. Layer three switches, sometimes referred to as routers, can forward packets based upon the destination network address. Layer three switches are capable of learning addresses and maintaining tables thereof which correspond to port mappings. Processing speed for layer three switches can be improved by utilizing specialized high performance hardware, and off loading the host CPU so that instruction decisions do not delay packet forwarding.
In addition, the switch fabric also plays an important part in the operational speeds of a network. Used with network switches, the fabric allows for the building of switching units with scalable port densities. The fabric receives switched data from network switches and needs to forward differing types of data (i.e. multicast, unicast, broadcast, etc.) to other connected network switches. However, prior art switch fabrics do not provide the needed throughput and can limit the total processing abilities of connected network switches.
The present invention is directed to a switch-on-chip solution for a self-routing fabric, capable of using ethernet, fast ethernet, and 1 gigabit and 10,000 Mbits/s ethernet systems, wherein all of the hardware is disposed on a single microchip. The present invention is also directed to methods employed to achieve the desired processing and forwarding of data. The present invention is configured to maximize the ability of packet-forwarding at linespeed, and to also provide a modular configuration wherein a plurality of separate modules are configured on a common chip, and wherein individual design changes to particular modules do not affect the relationship of that particular module to other modules in the system.
The present invention, in one embodiment, is directed to a method of forwarding data in a network switch fabric. An incoming data packet is received at a first port of the fabric and a first packet portion, less than a full packet length, is read to determine particular packet information, where the particular packet information includes an opcode value. A particular forwarding table of a plurality forwarding tables is read based on the opcode value and an egress port bitmap is determined based on entries read from the particular forwarding table. Finally, the incoming data packet is forwarded based on the egress port bitmap. The opcode value identifies whether the incoming data packet is a unicast packet, a multicast packet, a broadcast packet or resulted in a destination lookup failure. Through the use of the opcode value, one of a unicast forwarding table, a broadcast forwarding table, and a multicast forwarding table is read.
In addition, the method can also include determining whether the incoming data packet is to be mirrored, based on the particular packet information. Also, the step of determining an egress port bitmap can include determining if a destination for the incoming data packet is a trunked port, reading from a trunk group table, and deriving the egress port bitmap based on entries in the trunk group table. The method also allows for forwarding of the incoming data packet to a central computing unit when the opcode value is a certain value. Also, a class of service for the incoming data packet can be derived from the particular packet information and a priority for forwarding is set based on the class of service.
The present invention is also directed to a network switch fabric for forwarding data. The fabric includes at least one ingress port interface, having at least one ingress port and an ingress logic block that determines forwarding of packets. The fabric also has at least one egress port interface, having at least one egress port, where both interfaces are connected to a bus ring. A memory management unit and a packet pool memory connected to the memory management unit are also connected with the bus ring. The ingress logic block forwards a data packet based on an opcode value read from a header of the data packet. In addition, the ingress port interface includes a serializer/deserializer, a medium access controller and an ingress port map logic module. The memory management unit can also have a cell packer and a cell unpacker, wherein the cell packer groups packet data into cells to be stored in the packet pool memory and the cell unpacker separates stored cells before releasing the cells to the bus ring. The memory can also include an egress scheduler communicating with the cell unpacker, where the egress scheduler determines which packet data should be retrieved from the packet pool memory according to priority rules.